The present invention relates to a control system for a voltage-type inverter comprising a bridge connection of electric valves each comprising a reverse parallel connection of a semiconductor switching element and a diode and converting a DC power to an AC power by means of pulse-width modulation control (hereinafter referred to as PWM control).
FIG. 1 shows a conventional system. As shown, a DC power from a DC power source 1 is converted to an AC power by an inverter bridge 2 and supplied to a load motor 3, which, for the purpose of description, will be assumed to be an induction motor. The inverter bridge 2 comprises a bridge connection of electric valves each comprising a reverse parallel connection of a transistor 21-26 and a diode 31-36.
An inverter frequency setting device 4 provides a frequency reference voltage, which is applied to a ramp function generator 5, which limits the rate of change of the voltage. The output of the ramp function generator 5 is supplied to a voltage pattern generator 6, and an inverter output voltage pattern outputted by the voltage pattern generator 6 is supplied to an AC voltage reference circuit 8. The output of the ramp function generator 5 is converted, by a V/F converter (voltage-to-frequency converter) 7, to a frequency proportional to the inverter frequency. The AC voltage reference circuit 8 receives the voltage pattern output and the V/F converter output and produces voltage reference V*.sub.U, V*.sub.V, V*.sub.W. An oscillator 9 generates a trigonal wave e.sub.t for modulation. Comparators 10, 11, 12 compare the trigonal wave e.sub.t with the voltage references V*.sub.U, V*.sub.V, V*.sub.W, resepectively to produce PWM outputs PWM.sub.U, PWM.sub.V, PWM.sub.W, which are amplified by a drive circuit 13 and are used to drive the inverter bridge.
PWM control is well known, but, for an easier understanding of the invention, its fundamentals will be briefly discussed with reference to FIG. 2. Incidentally, today's control system often employs a microprocessor for the PWM operation, but the same principle is applied.
For the sake of simplicity, description is made with reference to one of the phases, e.g., phase U. Similar operations are performed with respect to other phases.
The U-phase voltage reference V*.sub.U, which is sinusoidal, is compared with the trigonal wave e.sub.t, and a PWM output PWM.sub.U is produced. The fundamental wave of the output PWM.sub.U is proportional to the voltage reference V*.sub.U. PWM control is accomplished by adjusting the magnitude and the frequency of the voltage reference V*.sub.U.
Typical examples of the switching elements used in the inverter bridge are thyristors, transistors, gate-turn-off thyristors (GTO's). These elements have more or less delay in switching, particularly in turn-off. Also this delay time is not precisely known and can vary depending on various factors. For this reason, it is necessary to take a measure for ensuring that, at no moment, the series connected switching elements, such as the transistors 21 and 24 in FIG. 1 are concurrently conductive. As such a measure, a dead time is provided so that the transistor 24 is turned on certain time after the transistor 21 is turned off. Further description on this point is given with reference to FIGS. 3 and 4.
FIG. 3 shows, in detail, part of the drive circuit 13 of FIG. 1 which relates to one of the phases, i.e., phase U. The PWM signal PWM.sub.U is passed through an on-delay circuit 132 which delays, by a delay time T.sub.D, only the leading edge of the signal pulse. The output signal V.sub.1 of the on-delay circuit 132 is amplified by a drive amplifier 134, whose output constitutes a drive signal V.sub.21 for the transistor 21. The signal PWM.sub.U is also fed to a logic circuit 131, where it is inverted to become a signal PWM.sub.U, and is then passed through an on-delay circuit 133, similar to the circuit 132. The output signal V.sub.2 of the on-delay circuit 133 is amplified by a drive amplifier 135, whose output constitutes a drive signal V.sub.24 for the transistor 24.
FIG. 4 shows the operation. The transistors 21, 24 are turned on and off by the signals V.sub.1, V.sub.2 whose leading edges are lagging behind PWM.sub.U, PWM.sub.U, respectively, by T.sub.D. The turn-on time of the transistors 21, 24 is not more than 1 .mu.sec. and can be neglected. On the other hand, the turn-off time t.sub.off of the transistors is several .mu.sec to several tens of .mu.sec. To make sure that simultaneous conduction of the series connected transistors 21, 24 be avoided, the delay time T.sub.D is set to be two to three times the turn-off time. As a result, there is a time interval when the transistors 21, 24 are both non-conductive, and during this time interval, the inverter output voltage is not definite. This point will be described with reference to FIG. 5.
The inverter output voltage V.sub.U-O is a voltage of the inverter U-phase output with reference to a neutral point 0 which is an imaginary mid-point which results when the DC power source 1 is imaginarily divided into two parts 1.sub.a and 1.sub.b. The inverter output line voltages can be derived, as is well known, from the differences between the voltages V.sub.U-O, V.sub.V-O, V.sub.W-O, i.e., the three output phase voltages on the respective output terminals with reference to the neutral point O.
Now attention is directed to the voltage V.sub.U-O across the inverter U-phase output terminal and the neutral point O. It is assumed that while the load current I is flowing in the direction (hereinafter referred to as the "positive direction") indicated by an arrow of a solid line in FIG. 6, the drive signal V.sub.24 for the transistor 24 falls (from on to off) at a time point t.sub.0. Because of the turn-off time t.sub.off of the transistor, the transistor 24 becomes actually non-conductive at a time point t.sub.1 (t.sub.off after t.sub.0). As a result, as shown in FIG. 5(f), the voltage V.sub.U-O is negative until t.sub.1. During the period from t.sub.1 to t.sub.2 when the transistor 21 becomes conductive, the transistors 21, 24 are both non-conductive. If the load current I continues to flow in the direction of the arrow of the solid line, no other circuit but one through the diode 34 is formed so that the terminal U has substantially the same potential as the negative terminal of the DC power source and the voltage V.sub.U-O is kept negative until t.sub.2. During the period t.sub.2 -t.sub.4 when the transistor 21 is conductive, the voltage V.sub.U-O is positive. During the period t.sub.4 -t.sub.5 when the transistors 21 and 24 are both non-conductive, the diode 34 becomes conductive again and the voltage V.sub.U-O becomes negative.
When the load current I is flowing in opposite direction, i.e., in the direction (hereinafter referred to as the "negative direction") indicated by an arrow of broken lines, the voltage V.sub.U-O assumes a waveform shown in FIG. 5(g). That is, while the transistors 21, 24 are both non-conductive, the load current I flows through the diode 31 into the DC power source 1 so that V.sub.U-O is positive during the period t.sub.1 -t.sub.2 and the period t.sub.4 -t.sub.5.
It is thus seen from FIGS. 5(f), (g) that the output voltage differs depending on the direction of the load current despite the fact that the same voltage is desired and attempted by PWM control.
Now consideration is given to variation of the inverter output voltage in relation to the load current in a situation where the load motor is an induction motor. In FIG. 7 the voltage reference V*.sub.U is indicated by a solid line while the actual inverter output voltage V.sub.U-O is indicated by a broken line. When the induction motor is under no load, the load current is, as shown in FIG. 7(a), lagging by about 90.degree.. During the period 0.degree.-90.degree. and 270.degree.-360.degree., the current is negative, so that the situation is like that of FIG. 5(g) and hence the actual inverter output voltage V.sub.U-O is higher (more positive) than the reference V*.sub.U. During the period 90.degree.-270.degree., the current is positive, so that the situation is like that of FIG. 5(f) and hence V.sub.U-O is lower (more negative) than V*.sub.U.
When the induction motor is under full load, the power factor of the load is higher and the larger portion (in terms of time) of the inverter output voltage suffers decrease, and the average voltage is decreased.
When the induction motor is in regenerative operation, the inverter output voltage is generally increased as shown in FIG. 7(c).
Thus, the inverter output voltage varies depending on the power factor of the load, or the phase of the current relative to the voltage. The amount of variation is substantially fixed regardless of the magnitude of the output voltage. As a result, the voltage regulation (change in the output voltage) is increased. In addition, the output voltage waveform is distorted (away from sinusoidal). Moreover, magnetic flux of the induction motor is varied because of the variation in the inverter output voltage, and the operation of the motor is unstable, and the efficiency of the motor is lowered because of the distorted current waveform, and torque ripple is increased.